Measuring Moore’s Law: Evidence from Price, Cost, and Quality Indexes
“Moore’s Law” in the semiconductor manufacturing industry is used to describe the predictable historical evolution of a single manufacturing technology platform that has been continuously reducing the costs of fabricating electronic circuits since the mid-1960s. Some features of its future evolution were first correctly predicted by Gordon E. Moore in 1965, and Moore’s Law became an industry synonym for continuous, periodic reduction in both size and cost for electronic circuit elements.
This paper develops develops some stylized economic facts, reviewing why and how this progression in manufacturing technology delivered a 20 to 30 percent annual decline in the cost of manufacturing a transistor, on average, as long as it continued. Other characteristics associated with smaller feature sizes would be expected to have additional economic value, and historical trends for these characteristics are reviewed. Lower manufacturing costs alone pose no special challenges for price and innovation measurement, but these other benefits do, and motivate quality adjustment methods when semiconductor product prices are measured.
Empirical evidence of recent changes to the historical Moore’s Law trajectory is analyzed, and shows a slowdown in Moore’s Law as measured by prices for the highest volume products: memory chips, custom chip designs outsourced to dedicated contract manufacturers (foundries), and Intel microprocessors. Evidence to the contrary, which relates primarily to Intel microprocessors is reviewed, as are economic reasons why Intel microprocessor prices might behave differently from prices for other types of semiconductor chips.
A computer architecture textbook model of how chip characteristics affect microprocessor performance is specified and tested in a structural econometric model of microprocessor computing performance. This simple econometric model, using only a small set of explanatory chip characteristics, explains 99 percent of variance across processor models in performance on commonly used performance benchmarks. This small set of characteristics should clearly be included in any hedonic model of computer or processor prices. Most of these chip characteristics also affect chip production cost, and therefore have an additional rationale for inclusion in a hedonic model that is separate from their demand-side effects on computer performance metrics relevant to users.
I am most grateful to Anjum Khurshid, Kevin Williams, Caroline Alexander, Pablo Cruzat, Javier Beverinotti, Manuel Chavez, Changgui Dong, and Miha Vindis for their excellent research assistance over the years this data was collected and maintained, and to financial support from the Kauffman Foundation, the National Science Foundation, and the International Monetary Fund. This research is based in part upon work supported by the National Science Foundation under Grant No. 0830389. I would also like to thank Ana Aizcorbe, David Byrne, Carol Corrado, Stephen Oliner, James Prieger, Marshall Reinsdorf, Steve Sawyer, Dan Sichel, Neil Thompson, and participants in the CRIW Measuring and Accounting for Innovation in the 21st Century” conference, and the IMF Fifth Statistical Forum, “Measuring the Digital Economy”, for their many useful comments on earlier versions of this paper. The views expressed herein are those of the author and do not necessarily reflect the views of the National Bureau of Economic Research.