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Measuring Moore's Law: Evidence from Price, Cost, and Quality Indexes

Kenneth Flamm


This chapter is a preliminary draft unless otherwise noted. It may not have been subjected to the formal review process of the NBER. This page will be updated as the chapter is revised.

Chapter in forthcoming NBER book Measuring and Accounting for Innovation in the Twenty-First Century, Carol Corrado, Jonathan Haskel, Javier Miranda, and Daniel Sichel, organizers
Conference held March 10–11, 2017
Forthcoming from University of Chicago Press
in NBER Book Series Studies in Income and Wealth

“Moore’s Law” in the semiconductor manufacturing industry is used to describe the predictable historical evolution of a single manufacturing technology platform that has been continuously reducing the costs of fabricating electronic circuits since the mid-1960s. Some features of its future evolution were first correctly predicted by Gordon E. Moore in 1965, and Moore’s Law became an industry synonym for continuous, periodic reduction in both size and cost for electronic circuit elements.

This paper develops develops some stylized economic facts, reviewing why and how this progression in manufacturing technology delivered a 20 to 30 percent annual decline in the cost of manufacturing a transistor, on average, as long as it continued. Other characteristics associated with smaller feature sizes would be expected to have additional economic value, and historical trends for these characteristics are reviewed. Lower manufacturing costs alone pose no special challenges for price and innovation measurement, but these other benefits do, and motivate quality adjustment methods when semiconductor product prices are measured.

Empirical evidence of recent changes to the historical Moore’s Law trajectory is analyzed, and shows a slowdown in Moore’s Law as measured by prices for the highest volume products: memory chips, custom chip designs outsourced to dedicated contract manufacturers (foundries), and Intel microprocessors. Evidence to the contrary, which relates primarily to Intel microprocessors is reviewed, as are economic reasons why Intel microprocessor prices might behave differently from prices for other types of semiconductor chips.

A computer architecture textbook model of how chip characteristics affect microprocessor performance is specified and tested in a structural econometric model of microprocessor computing performance. This simple econometric model, using only a small set of explanatory chip characteristics, explains 99% of variance across processor models in performance on commonly used performance benchmarks. This small set of characteristics should clearly be included in any hedonic model of computer or processor prices. Most of these chip characteristics also affect chip production cost, and therefore have an additional rationale for inclusion in a hedonic model that is separate from their demand-side effects on computer performance metrics relevant to users.

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This chapter first appeared as NBER working paper w24553, Measuring Moore’s Law: Evidence from Price, Cost, and Quality Indexes, Kenneth Flamm
 
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